* LSTTL input logic compatible
  – VIL(max) = 0.8 V, VIH(min) = 2 V
* CMOS input logic compatible
  – II ≤ 1 µA at VOL, VOH
* Buff.

* Alarm / tamper detect circuit
* S-R latch 3 Description This device contains four independent 2-input NAND ga.

This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A
* B in positive logic. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) CD74HCT132M SOIC (14) 8.65 mm × 3.90 mm CD74HCT132E .

CD54HCT132J

CD54HCT138

CD54HCT138F

CD54HCT139

CD54HCT10

CD54HCT109

CD54HCT10F

CD54HCT11

CD54HCT112

CD54HCT123

CD54HCT125

CD54HCT126

CD54HCT14